The PDP (Plasma Display Panel) and the LCD (Liquid Crystal Display) are now drawing public attention as a thin and lightweight display device. The display device of this type is directly driven by the digital signal, and so it requires a PLL for generating the system clock for the digital processing such as the A/D (Analog/Digital) conversion. Such a PLL is required to provide not only stable and accurate performance but also a wide clock range.
The conventional PLL circuit, as seen from FIG. 1, comprises a phase comparator 11, for comparing the reference signal REF (e.g., horizontal synchronizing signal) and a comparison signal VAR to output a phase difference signal Ph at any one of 3 levels according to the phase difference, an LFP (Low-Pass Filter), for converting the signal Ph outputted from the comparator 11 into a control voltage, a VCO (Voltage Control Oscillator) 14, for outputting to an output terminal 13 the clock whose frequency is controlled by the control voltage outputted from the LPF 12, and a loop counter 15, for dividing the frequency of the clock into 1/N (N: an integer) for feeding it back to the phase comparator 11.
The phase comparator comprises, as shown in FIG. 2, a first D flip-flop 1 (hereinafter referred to as "1D-FF"), for receiving an H-level signal (e.g., an H-level signal supplied from a Vcc power source through a pull-up resistor), which is inputted to its data terminal at an up-edge (at a rise) of a reference signal REF, which is inputted to its clock terminal, and storing the H-level signal as a Q1 output, a second D-FF 2, for receiving the H-level signal, which is inputted to its data terminal at the up-edge of a comparison signal VAR, for storing it as Q2 output, an exclusive OR gate 3, for outputting a signal Xo representing an exclusive "or" of the Q1 output of the first D-FF 1 and the Q2 output of the second D-FF 2, a 3-state inversion buffer 4, for receiving the Q2 output of the second D-FF 2 as an input signal and the output signal of the exclusive OR gate as the gate control signal Xo to output the signals of three different state, namely, H-level, L-level and Ni-Z (high impedance) as phase difference signals Ph and an NAND gate 5, for outputting a signal Na as an inverted AND signal based on the Q1 output of the first D-FF 1 and the Q2 output of the second D-FF 2.
When there is a large phase difference between the reference signal REF and the comparison signal VAR (e.g., when the phase of the reference signal VAR delays by about 4 clocks from the that of the reference signal), this produces the effect as represented by period T1 on the left-hand side in FIG. 3. That is, as shown in FIGS. 3(a) and (b), when the phase of the comparison signal VAR delays largely from that of the reference signal REF, the Q1 and Q2 outputs respectively from the first D-FF 1 and the second D-FF 2, the signal Na outputted to the reset terminals of the first D-FF 1 and the second D-FF 2 from the NAND gate 5 and the gate control signal Xo outputted from the exclusive OR gate are as shown in FIGS. 3(c), (d), (e) and (f), and thus the phase difference signal Ph outputted from the 3-state inversion buffer 4 becomes H-level (delayed phase condition) during the period Td corresponding to the phase difference as shown in (g) of the figure, causing the frequency of the clock outputted from the VCO 14 to increase by the control voltage (voltage corresponding to that has enabled the H-level to continue for period Td).
When there is a large phase difference between the reference signal REF, that is, when the phase of the comparison signal VAR is leading the phase the phase of the reference signal, the phase difference signal Ph outputted from the 3-state inversion buffer 4 becomes L-level (advanced phase state), causing the frequency of the clock outputted from the VCO 14 to decrease according to the control voltage (voltage corresponding to the continuation of L-level for the period Td) outputted from LPF 12.
Further, when the reference signal REF is omitted for some reason, the omission of the reference signal REF is detected by a circuit (not shown) to generate the reference signal which has been omitted and to input the generated reference signal REF to a phase comparator 11 through its input terminal 10, thereby preventing the occurrence of any large phase difference between the reference signal REF and the comparison signal VAR to be inputted to the phase comparator 11.
However, in the case of the prior art shown in FIG. 1, the omission of the reference signal REF is compensated by inputting the omission compensation signal to the phase comparator 11 through its input terminal 10, and, in consequence, the control voltage is applied to the VCO 14 corresponding to the phase difference during the period from the omission of the reference signal REF to the supply of the omission compensation signal. This gives rise to a problem that it is difficult to supply stable clock if VCO 14 having a very wide frequency variation range is used.
Further, where the phase difference between the reference signal and the comparison signal is approximate to 0, if there occurs a time lag between the phase information (phase information Q1 and phase information Q2) and the gate control signal Xo from the 3-state inversion buffer 4, this causes a problem that the phase difference signal Ph accurately corresponding to the phase difference cannot be obtained from the output side of the 3-state inversion buffer 4.
Also, there has been another problem that too small phase difference causes the 3-state inversion buffer 4 to become unable to respond to such a small phase difference.
For instance, as represented by the period T2 on the right-hand sides in FIGS. 3(a) and (b) respectively, when the phase of the comparison signal VAR delays slightly from the phase reference signal REF, the H-level period td of the gate control signal Xo, to be outputted to the 3-state inversion buffer gate 4 from the exclusive OR gate, becomes as short as the period shown in (f) of the same figure. In consequence, there occurs a time lag between the phase information (Q1, Q2) and the gate control signal Xo due to the delay of the transmission of the signal, and, when the phase information Q1 and Q2 will not vary as represented by the waveforms on the right-hand sides of FIGS. 3(c) and (d), the phase difference signal Ph, outputted from the 3-state inverse buffer 4, remains in the state represented by Hi-Z shown in (g) of the same figure, causing a problem that the phase difference signal corresponding to the phase difference cannot be obtained.
Therefore, as shown in FIG. 4, the control voltage corresponding to the phase difference cannot be obtained near the phase difference of 0, causing the occurrence of jittering and the resulting difficulty in supplying stable clock when the VCO 14 having an extremely wide frequency variation range is used.
The present invention is made in consideration of the above problems of the prior art and is designed to provide a PLL circuit capable of supplying stable clock even when a VOC having a very large frequency variation range.
More particularly, the object of the present invention is to provide a PLL circuit capable of supplying stable clock by effectively compensating for the omission of the reference signal even when a VOC having a very wide frequency variation range is used.
Further, another object of the present invention is to provide a PLL circuit capable of outputting an accurate phase difference signal corresponding to the phase difference to the VOC side from the phase comparator in order to supply stable clock even when the phase difference between the reference signal and the comparison signal is close to 0 even in the case where a VOC having a very wide frequency variation range is used.